Graphics display systems typically employ a graphics controller chip between a host CPU and a graphics display device, such as an LCD panel. Generally, such systems also include one or more peripheral devices. For example, in cellular telephones it is becoming increasingly common to couple a camera peripheral to the graphics controller. Both the camera and the host CPU are capable of providing corresponding sets of image data. The graphics controller can select between the sets of data for provision to the display device, or the graphics controller can overlay one set of data on the other set of data for provision to the display device.
Where the peripheral is a camera, the graphics controller receives image data from the peripheral. Alternatively, the graphics controller could provide data to the peripheral. In either case, data exchanged between the graphics controller and the peripheral must typically be level shifted because the graphics controller and the peripheral are typically powered at different voltage levels. Accordingly, the graphics controller includes a level shifter for, e.g., each bit of a parallel data bus. The level shifters are typically formed of CMOS technology.
The graphics controller includes a pin for receiving power from the peripheral to provide to one side of each level shifter with power while, internally, power used by the graphics controller is provided to the other side of the level shifters. So long as the power from the peripheral is “on,” the level shifters function normally.
On the other hand, damage to the level shifters can result from CMOS latch-up if the peripheral is powered down while the graphics controller remains powered up. Yet it is often desired to power down the peripheral while the graphics controller remains powered up, for example, to reduce power consumption when processing an image received from the peripheral.
This problem has been solved by providing a power cut-off protection circuit in the graphics controller. The power cut-off protection circuit is controlled by another circuit that includes a register to which the host CPU writes at substantially the same time that the host CPU powers down the peripheral. The contents of the register are used to turn on respective MOSFETs connecting the level shifters to ground. This prevents CMOS latch-up in the level shifters when the power from the peripheral is cut-off.
This solution to the problem is not complete. If the graphics controller is reset any time that the peripheral power is off, the contents of the register are lost with the consequence that the MOSFET is turned back off, thus exposing the level shifters to the problem which the cut-off circuit was intended to solve.
Accordingly, there is a need for a circuit and method for controlling a power cut-off protection circuit that provides for more robust protection than has been provided in the prior art.